1. Field of the Invention
The invention relates to IBM PC AT-compatible computer architectures, and more particularly to I/O interfaces for communicating with peripheral devices.
2. Description of Related Art
The IBM PC AT-computer architecture has become an industry standard architecture for personal computers. The typical IBM PC AT-compatible computer includes an I/O bus, sometimes referred to in these systems a s a n AT bus. Such a bus is used to interface communications between a host and a peripheral device, or communications between peripheral devices and host memory.
The most commonly used I/O bus is the industry standard architecture (ISA) bus. The ISA bus was adopted by several computer industry groups to create a standard to permit the development of compatible add-on cards in a reasonable and consistent fashion. The ISA bus includes 8 or 16 data lines in a data bus, address lines in an address bus distinct from the data bus, as well as distinct control and command lines.
The various signals on the ISA bus are well specified and well known in the industry. General information on the ISA bus can be found in Solari, "AT Bus Design" (San Diego, Annabooks, 1990), incorporated by reference herein. For present purposes, the following signals are important:
______________________________________ SA(23:0) 24 address lines. BALE Bus address latch enable line. In a CPU initiated I/O bus cycle, this line indicates when the SA address, AEN and SBHE# lines are valid. In other I/O bus cycles, the platform circuitry drives BALE high for the entire cycle. SBHE# System byte high enable. When SBHE# is active and SA(0) is low, then a 16-bit access will be performed. AEN Address enable line. When active, informs I/O resources on I/O bus to ignore the address and I/O command signals. Used primarily in DMA cycles where only the I/O resource which has requested and received a DMA acknowledgment signal (DACK#) knows to ignore AEN and respond to the I/O signal lines. SD(15:0) 16 data lines. MEMR#, Read request lines to a memory SMEMR# resource on the I/O bus. SMEMR# is the same as MEMR# except that SMEMR# becomes active only when the read address is below 1 MB (i.e., SA(23:20) = 0). Also called MRDC# and SMRDC#, respectively, or MRD# and SMRD#, respectively. MEMW# Write request lines to a memory SMEMW# resource on the I/O bus. SMEMW# becomes active only when the write address is below 1 MB. Also called MWTC# and SMWTC#, respectively, of MWR# and SMWR#, respectively. IOR# Read request line to an I/O resource on the I/O bus. Also called IORC# or IORD#. IOW# Write request line to an I/O resource on the I/O bus. Also called IOWC# or IOWR#. MEMCS16# Memory chip select 16. Asserted by an addressed memory resource on the I/O bus if the resource can support a 16-bit memory access cycle. Also called M16#. IOCS16# I/O chip select 16. Asserted by an addressed I/O resource on the I/O bus if the resource can support a 16-bit I/O access cycle. Also called IO16#. SRDY# Synchronous Ready line. Also sometimes called OWS#, NOWS# or ENDXFR#. Activated by an addressed I/O resource to indicate that it can support a shorter-than-normal access cycle. In an ISA system, only the platform CPU can execute a no- wait-state cycle. IOCHRDY I/O channel ready line. If this line is deactivated by an addressed I/O resource, the cycle will not end until it is reactivated. A deactivated IOCHRDY supersedes an activated SRDY#. Also sometimes called CHRDY. RESET Minimum pulse width of 1 microsecond. IRQ(15, 14, Interrupt request lines to 12:9, 7:3) interrupt controller for CPU. DRQ(7:5, DMA Request lines from I/O 3:0) resource on I/O bus to platform DMA controller. DACK(7:5, DMA Acknowledge lines. 3:0) TC DMA terminal count signal. Indicates that all data has been transferred. Also called T/C. BCLK I/O bus clock signal. 6-8.33MHz square wave. ______________________________________
Recently, efforts have been made to develop other bus protocols for PC AT-compatible computers with the goals of reducing the size of PC AT-compatible computers as well as continued industry standardization. These efforts have included the development of the PCI local bus as well as the PCMCIA bus.
The PCI local bus has been developed to establish an industry standard for local bus architectures, particularly those interfacing with high bandwidth functions. The PCI local bus is described in detail in "PCI Local Bus Specification", Revision 2.0 (Hillsboro, Oreg., PCI Special Interest Group, 1993), incorporated by reference herein. The PCI local bus attempts to reduce the number of pins required for a local bus design by multiplexing address information and data information onto a single address-data bus. However, the PCI local bus still requires a minimum of 47 pins to provide adequate communication between a processor and local components, with its address-data bus comprising 32 of those pins and various command information comprising at least 4 pins. Further, because the PCI bus was designed primarily to support high-end peripherals, it is not as economical to manufacture low-end peripherals for the PCI-bus as it is for the older, slower, ISA-bus.
The PCMCIA bus has been developed to promote the interchangability of integrated circuit cards among a variety of computer types and products, including IBM PC-compatible systems. The PCMCIA bus is described in detail in Personal Computer Memory Card Int'l Assoc. (PCMCIA) "PC Card Standard", Revision 2.0 (Sunnyvale, Calif., 1991), incorporated by reference herein. The PCMCIA bus attempts to reduce the size of the I/O interface by miniaturizing the connector. However, PCMCIA does little toward actually reducing the number of pins required to utilize its bus over ISA. The PCMCIA connector requires 68 pins, including 26 pins for addressing functions and 16 separate pins for data.
Therefore, despite these attempts to develop other bus protocols, the ISA bus interface remains one of the most widely used and accepted I/O bus architectures. While it is important from an interfacing perspective to maintain the industry standards to maintain overall system compatibility for various add-on cards designed in compliance with industry standards, it is also desirable to reduce the pin counts on interface connectors, and thus reduce the size of PC AT-compatible computers and their add-on peripheral devices.